Ultra Efficient Computing Energy Systems

Ultra-efficient computing energy systems means the energy cost of computation and the honest inventory of what can be done about it: the thermodynamic bound on erasing a bit, the efficiency of real silicon against that bound, the facility overhead wrapped around the silicon, the electricity the resulting industry actually draws, and the alternative architectures — reversible, adiabatic, superconducting, neuromorphic, analogue in-memory, thermodynamic — that are offered as ways past the current numbers.

The slot sits in Energy Systems rather than in computing, and that placement fixes the question. It is not whether chips get faster or whether a new device physics is elegant. It is whether the electricity demand of computation is a genuine energy-system problem, how much of it efficiency can absorb, and where the physical floor really is as opposed to where it is rhetorically placed.

The scope boundary is worth stating precisely, because this topic bleeds into half the map. This brief owns the demand side: joules per operation, watts per rack, the ratio of facility energy to computing energy, the terawatt-hours the sector consumes, and every claim that a new device reduces any of those. It does not own the supply side. Small modular reactors, geothermal megaprojects, energy storage revolutions and energy corridors all now aim a substantial share of their commercial case at this load, and what they can deliver is their argument to make. The arbitration rule where they meet is direction of travel: if the question is how many joules a computation costs, it belongs here; if the question is where the joules come from, it belongs there.

Two further boundaries. Superconducting logic is treated here, because the interesting result about it is an energy-accounting result rather than a materials result; the conductor itself belongs to high temperature superconductors and the installed hardware to superconducting infrastructure. And computation performed in living substrates belongs to biological computing, which shares this brief's interest in radical substrates and none of its arithmetic.

One warning before any number appears. Data-centre energy figures are among the least reliable quantities in public technical discussion, not because anyone is lying but because the boundaries differ. A figure may or may not include the network the data centre talks to, cryptocurrency mining, the embodied energy of the hardware, the water, and the idle capacity held in reserve. Two credible estimates of the same year can differ by a factor of two purely on scope. This brief states the boundary, the year and the reporting party's interest with every terawatt-hour figure it quotes, and where the literature disagrees it says so rather than picking a winner.

Established The thermodynamic floor is real and precisely known. Landauer's bound is kT ln 2 per logically irreversible bit erasure. With Boltzmann's constant at 1.380649 × 10⁻²³ J/K and T = 300 K, kT is 4.14 × 10⁻²¹ J and the bound is 2.87 × 10⁻²¹ J, about 2.9 zeptojoules. There is no arithmetic dispute about this figure anywhere in the literature consulted.

Established And the bound is far narrower than it is usually made to carry. It applies only to logically irreversible bit erasure. It is not a bound on an operation, not a bound on a floating-point calculation, and not a bound on moving data from one place to another. Most of a modern chip's energy goes into charging and discharging interconnect capacitance and into leakage current, and neither of those is thermodynamically required to dissipate anything at all. Distance from Landauer is therefore a rhetorical measure rather than a headroom measure, and that single distinction reorganises the whole subject.

Established The distances, with the basis stated, because a ratio without a stated basis is unfalsifiable. Switching one CMOS gate costs between 100 attojoules and 100 femtojoules, which is 3.5 × 10⁴ to 3.5 × 10⁷ times the bound. One 16-bit floating-point operation costs about 150 fJ, roughly 5 × 10⁷ times. Communicating one bit across a chip costs about 600 fJ, roughly 2 × 10⁸ times — note that moving a bit costs four times what computing with one costs. And an H100 measured whole-chip at 1.4 × 10¹² FLOP/J works out to 714 fJ per delivered operation, about 2.5 × 10⁸ times the bound. The defensible headline is therefore about 10⁵ per elementary gate switching event and about 10⁸ per useful whole-chip floating-point operation. The energy figures are sourced; the ratios are this brief's arithmetic on them. Jeffrey Bokor, who ran the nanomagnet erasure experiment, summarises real computers as “probably on the order of a million times more energy per operation” — the middle of that range, and a useful check that the spread is a definitional spread rather than a disagreement.

Frontier Now the number that actually constrains the energy system, and it is the one the framing of this topic tends to bury. The reachable CMOS ceiling is about two hundred times, not a hundred million. The same first-principles analysis that supplies the per-operation figures estimates maximum achievable CMOS efficiency at 4.7 × 10¹⁵ FP4/J and 2.9 × 10¹⁴ FLOP/J at 16-bit precision — roughly 200× better than current microprocessors — and attaches to it a stated 50% chance that improvements cease before even that is reached. Flagged frontier rather than established because the source is a research institute rather than a peer-reviewed venue, and because the pack could not obtain the canonical Horowitz energy-per-operation table to cross-check it. The gap between what physics permits and what engineering can reach is itself about six orders of magnitude.

Established The clearest proof that device-level energy is the wrong metric comes from superconducting logic, and it is the result that should anchor how every other claim in this brief is read. Rapid single flux quantum logic switches a Josephson junction at 0.25 attojoules at a critical current of 0.175 mA — between 400 and 400,000 times below CMOS gate energy, and only about 6.2 × 10³ above its own Landauer bound at 4.2 K, where kT ln 2 is 4.0 × 10⁻²³ J. Then apply the refrigerator. Cryogenic inverse efficiency at 4.2 K runs from 352× at an optimistic Carnot fraction of 0.2 to 3,520× at a realistic 0.02. A worked 1.4-billion-junction processor at 4 GHz dissipates 0.71 W cold and draws 250 W to 2.5 kW at the wall — three to thirty times more than the equivalent CMOS processor. Measured superconducting floating-point units come out at 0.12 to 1.3 GFLOP/J against CMOS at 2.27 GFLOP/J, two to twenty times worse. A device-level victory of five orders of magnitude, converted into a system-level defeat, entirely by the plant required to keep the device in its winning regime. In computing energy systems, the device is never the system.

Established On the facility side, the work is essentially finished. Power usage effectiveness — total facility energy divided by energy delivered to the computing equipment — averaged 1.54 across the industry in 2025, the sixth consecutive year in which the headline figure has virtually stood still, on a self-reported industry survey. An independent national-laboratory model of the United States fleet lands on the same 1.54 for 2023 from a different method. The best hyperscale operator reports a trailing-twelve-month fleet figure of 1.09, and has been between 1.08 and 1.12 since 2018. So: if the entire global fleet instantly became the best operator on Earth, total data centre electricity would fall by 1 − 1.09/1.54, which is 29%. At the 2025 growth rate of 17% a year, that entire one-off prize is consumed in 2.2 years. The arithmetic is this brief's; the inputs are sourced.

Established The mechanism that made computing look energy-free between 2010 and 2018 was a set of one-off transitions, and they have run. Over that period global data centre compute instances rose more than 550%, storage capacity rose twenty-fivefold and network traffic more than tenfold, while electricity went from 194 TWh to 205 TWh, a 6% increase — energy per compute instance falling about 6.1×, roughly 25% a year compounded. The named mechanisms were a fourfold reduction in electricity per volume-server computation, a ninefold reduction in watts per terabyte of storage, a fivefold increase in compute instances hosted per server through virtualisation, and migration to hyperscale facilities with lower overhead. Three of those four are transitions with an endpoint: virtualisation consolidation, hyperscale migration, and facility overhead. Only server-silicon efficiency continues, and it is the one bounded at about 200×. The successor national-laboratory report states the conclusion in a sentence worth quoting exactly: the expansion of data centre services into areas requiring new hardware has “ended the era of generally flat data center energy use.”

Established And demand is now compounding faster than efficiency can absorb. Global data centre electricity reached 415 TWh in 2024, about 1.5% of world electricity, and 485 TWh in 2025, a 17% year-on-year rise against global electricity demand growth of 3%; AI-focused data centres grew 50% in 2025 alone. Splicing the 2018 peer-reviewed figure to the 2025 intergovernmental one gives about 13.1% a year across 2018–2025, against 0.7% a year across 2010–2018 — and that splice crosses a boundary change, which is flagged rather than smoothed. At 13 to 17% a year, the entire 200× CMOS ceiling is consumed in roughly three to four decades.

Frontier The rebound is visible inside a single firm's own accounts, and it is the strongest empirical anchor available. One hyperscaler reports a 33× reduction in energy per median text prompt over one year from its own production measurement, and in the same period reports a 37% annual increase in electricity demand, its largest load growth in history, with operational emissions down 2% and supply-chain emissions up 25%. Both numbers are self-reported by an interested party, and both are disclosed against interest. This is not proof of causation and this brief does not claim it is. It is the clearest documented instance of per-unit efficiency in computing failing to translate into reduced absolute consumption.

So the position is not that computing sits a hundred million times above a physical floor with room to run. It is that the reachable engineering ceiling is about two hundred times, the historically decisive efficiency mechanisms were structural one-offs now spent, facility overhead is essentially wrung out, and demand compounds at 13 to 17% a year. The binding constraint is the rate of demand growth against the rate of efficiency improvement, and every exotic alternative examined below currently loses at the system level even where it wins at the device level.

Established Photonics enters this brief twice, and only one of the two entries has a number attached to a shipping product. The first is optical input/output: replacing the electrical serialiser-deserialiser links between packages with light carried from inside the package. In March 2025 NVIDIA announced co-packaged-optics networking switches claiming 3.5× better power efficiency and 10× better network resiliency than pluggable-transceiver switching; Broadcom has made claims of a similar shape for its own co-packaged parts. Frontier Published energy figures for the link itself run roughly 15 to 30 pJ per bit for pluggable optics at current rates, with co-packaged designs targeting low single digits. Every one of those numbers is vendor-reported and none has an independent measurement behind it — which is the same audit gap this brief documents for power usage effectiveness, arriving in a new product category.

Frontier Do the system arithmetic before believing the multiplier, because the multiplier applies to a minority share. Interconnect — switches plus optics — is commonly put at roughly 10 to 20% of IT power in a large accelerator cluster. Take the upper end and the most generous vendor claim together: removing 70% of a 20% share is a 14% cut in IT power, and less than that at the facility meter once cooling and distribution are included. That is a real and worthwhile saving of roughly the size of one good power-usage-effectiveness campaign, and it is not a new efficiency regime. Speculative The stronger case for optical I/O is not joules at all but reach: it decides how large a coherent training domain can be built before the network becomes the bottleneck, which changes what gets built rather than what a built thing costs to run.

Established The second entry is photonic computing proper, and its headline energy claim is true about the wrong boundary. A matrix-vector multiply performed in an interferometer mesh or a microring bank is close to passive: the multiplication happens as light propagates, so the marginal energy of the arithmetic itself can be quoted below a femtojoule per operation. Established The energy is not in the arithmetic. It is in the digital-to-analogue converters that drive the modulators, the analogue-to-digital converters that read the photodetectors, the laser that supplies the light, and the thermal control that keeps the optical components on resonance. Frontier Integrated laser wall-plug efficiency is typically in the 10 to 30% band, so every optical joule delivered costs three to ten electrical ones before any computing happens. This is precisely the failure mode this brief already records for analogue in-memory computing, in a different substrate: the tile is efficient, the tile is not the system, and the gap is conversion and peripherals. Photonics does not introduce a new problem so much as supply a second independent instance of one this brief already names.

What is genuinely open in this field is narrower than the coverage suggests, and the way to separate the two is to ask of every claim whether the number quoted was measured, on what workload, and at what system boundary. Applied consistently, that question empties most of the field's headline figures and leaves a small set of real results behind.

Established Reversible and adiabatic computing is the theoretically correct answer, and as of 2026 it has real silicon and no system win. Computation that does not erase does not owe the erasure tax, so a reversible machine is not bounded by kT ln 2 in the way an irreversible one is. The furthest-developed effort announced a tape-out in January 2025 claiming 50% energy recovery in the resonator circuit; at that point, in May 2025, the chips were still in transit from fabrication and the 50% was a simulation that had not been independently verified. Then in September 2025 came the measurement: a 22 nm CMOS test chip at 500 MHz, containing a capacitor array, a shift register and reversible logic gates, with measured energy recovery factors of 1.77× and 1.41× respectively. That is a genuine result on fabricated silicon and it deserves the credit. It is also not a comparison: no absolute energy per operation against a conventional part is published, and a recovery factor inside a resonator at 22 nm and 500 MHz is a long way from beating a 3 nm production chip on joules per useful operation.

Handwave The 4,000× figure attached to that programme. Its own trade-press account places it “on the road map but probably 10 or 15 years out.” It is a target, and this brief records it as one. The pack was unable to fetch the 2025 APL Electronic Devices industry perspective on the limits of conventional CMOS and the need for adiabatic reversible computing; it is named here as an unverified source whose contents were not read, and it is likely authored by parties with a commercial stake.

Frontier Superconducting digital logic has a live counter-claim to the negative result in the position section, and it deserves to be stated rather than smoothed. Yokohama National University's adiabatic quantum-flux-parametron four-bit “MANA” microprocessor switches a junction at 1.4 zeptojoules — about 35 times its own 4.2 K Landauer bound, which is remarkably close — and the team claims it is about 80 times more energy-efficient than state-of-the-art semiconductors even after including cooling from room temperature to 4.2 K. The catch is the clock. The demonstrated processor ran at 100 kHz; a separate execution unit reached 2.5 GHz. At 100 kHz the throughput is four to five orders of magnitude below a CMOS core, so a per-operation comparison is not a per-second comparison, and the result is from 2020 rather than the current period. This brief reports the disagreement between the RSFQ accounting and the AQFP claim and does not resolve it.

Handwave The 2025 state-of-the-art review of superconducting digital circuits, and the shape of its silence. A peer-reviewed September 2025 review by the people building the hardware documents a fabricated coarse-grained reconfigurable array prototype, a temporal decimal multiplier and a convolutional accelerator achieving comparable peak performance in 32 times less area than its predecessor, and asserts significant potential for reducing energy consumption relative to room-temperature CMOS — while giving no energy-per-operation figures and no net system-level comparison including cooling. The absence of the cooling arithmetic, in a 2025 review whose authors have a programme stake, is itself informative. The most recent quantitative net-of-refrigeration treatment this brief could find dates from 2016.

Frontier Neuromorphic computing's most useful source is the field's own assessment of itself, and it is unusually candid. A 2025 peer-reviewed review with eighteen authors from academia and industry states that the “lack of such formal theoretical advantages on important problems has been one challenge in building interest in neuromorphic computing,” and that identifying metrics and benchmarks “remains a notable challenge.” The only concrete quantitative energy claim in it is a research chip's better-than-three-orders-of-magnitude energy–delay product against conventional solvers — on optimisation problems, not on mainstream AI. A companion benchmarking paper with more than eighty authors puts it more bluntly still: the field “currently lacks standardized benchmarks,” and without them “the validity of neuromorphic solutions cannot be directly quantified.” That is the field, in a peer-reviewed journal, saying its own energy claims are not currently verifiable in a comparable way.

Established The best-measured neuromorphic result is real and narrow. Sixteen inference chips in a 2U server over PCIe, running a three-billion-parameter language model, measured 28,356 tokens per second at under 1 ms per token, 72.7 times more energy-efficient than the next-lowest-latency GPU and 46.9 times faster than the next most energy-efficient GPU. Established as a measurement, and reported by an interested party whose comparison GPUs are unnamed. The architectural caveat matters more than the vendor caveat: the approach holds all weights in on-chip SRAM, fourteen transformer layers per card, which does not extend to frontier-scale models or to long-context key-value caches.

Frontier Analogue in-memory computing has the same shape: measured gains that are smaller than the headline and workloads that are narrower. A peer-reviewed 2023 phase-change-memory chip measured 12.4 TOPS/W chip-sustained and 6.94 TOPS/W as a full-system estimate on a speech-to-text benchmark with 45 million weights across more than 140 million devices — at an accuracy cost of 9.258% word error rate against a 7.452% software baseline, and with the joint layer, all vector–vector products, biases and nonlinear activations running on a host machine. Against an H100 at roughly 1.4 to 2.8 TOPS/W at INT8, that is a two- to fivefold advantage on a favourable workload with accuracy loss and off-chip help, not orders of magnitude. A December 2025 peer-reviewed tile perspective reports 20.5 to 65.0 TOPS/W for phase-change tiles, about 11.9 to 195.7 for resistive memory and up to 351 for SRAM — and its authors are explicit that analogue-to-digital conversion and digital overhead are the unresolved bottleneck between tile-level and system-level efficiency. The 12.4 → 6.94 step is the size of that discount before the host is even counted.

Frontier The archetypal number in this field, and worth naming as such. A September 2025 peer-reviewed paper in a Nature-family journal reports gain-cell in-memory attention with up to a 70,000-fold reduction in energy and a 100-fold speed-up against an H100, at accuracy comparable to GPT-2 — and states that the study uses device-level simulations to evaluate design performance. Nothing was fabricated and nothing was measured, for one kernel, against a model architecture from 2019. This brief could not read the methods section directly, so that statement rests on the authors' own summary sentence.

Frontier Thermodynamic computing has real circuits, simulated architectures and toy benchmarks. The probabilistic-bit silicon is genuine and novel: an experimental thermodynamic random-number-generator chip exists and has been measured. The 10,000× figure attached to it comes from a December 2025 preprint that describes its own result as coming from “a combination of measurements from real circuits, physical models, and simulations,” in which the architecture being evaluated is simulated rather than built and the workload is binarized Fashion-MNIST image generation. The company's own writing says it plainly — running these models on its hardware “could be 10,000x more energy efficient… as shown by our simulations” — and its hardware page describes the fabricated chip without giving an energy-per-sample figure. A second company taped out a thermodynamic chip in August 2025 claiming “up to 1,000x energy consumption efficiency” against traditional semiconductors, projected rather than measured, with the chip uncharacterised at announcement.

Handwave Both figures, as efficiency claims about AI workloads. As of the research date, no thermodynamic computing device has a published measured end-to-end energy figure on any real workload. The circuits are frontier; the multipliers are handwave.

Frontier The genuinely open physics question is smaller and more interesting than any of the above. It is what the March 2026 erasure measurement in silicon DRAM cells implies for real memory, and it is treated in the experiments section: the first attempt to measure Landauer in an actual memory technology found a constraint that is tighter than kT ln 2 and that arises from the device architecture rather than from thermodynamics.

Frontier Is there a workload where an optical processor beats a contemporaneous digital accelerator in joules per token, measured at the wall, with the laser and the converters inside the boundary? No such published comparison was located for this pass. Handwave The thousandfold and ten-thousandfold claims that circulate for photonic accelerators are the same species as the thermodynamic-computing claims this brief already dismantles: a device-level ratio extrapolated to a system, against a baseline the claimant chose. Speculative The workload fit that would most plausibly survive an honest accounting is inference with heavy weight reuse — the same optical weights illuminated by many input vectors — because that is the only regime where the cost of getting data into and out of the optical domain is amortised rather than paid per operation.

Frontier Precision is the constraint most often left out of the workload-fit argument. An optical multiply is analogue, and effective precision after noise, crosstalk and detector shot noise is usually reported in the four-to-eight-bit range rather than at the bit-exact widths training requires. Speculative That points the technology at inference and at problems tolerant of stochastic error, and away from training, which is where the energy actually is. Frontier A separate branch takes the analogue character as the point rather than the price: an analogue optical computer reported by an industrial laboratory in 2025 targets fixed-point-iteration and optimisation problems rather than general matrix multiplication, which is a narrower and more defensible claim than a general-purpose accelerator.

Established The first bottleneck is the rate of demand growth against the rate of efficiency improvement, and everything else in this brief is subordinate to it. Demand is compounding at roughly 13% a year across 2018–2025 and 17% in 2025 alone. The full remaining reachable CMOS improvement of about 200× is consumed by roughly three to four decades of that growth, and the entire remaining facility-overhead prize is consumed in about 2.2 years. Efficiency is not competing with the level of demand; it is competing with the derivative, and it is losing.

Established The second is that the historical efficiency mechanism was a set of transitions rather than a trend, and it is spent. Virtualisation delivered a fivefold increase in compute instances per server; hyperscale migration delivered lower overhead; facility overhead itself delivered the rest. Each has an endpoint and each has reached it. Only server-silicon efficiency continues, and it is the bounded one. A national laboratory has stated in terms that the era of generally flat data centre energy use has ended, with the mechanism named: growth in accelerated servers more than doubled total demand between 2017 and 2023.

Established The third is that facility overhead is essentially wrung out. Industry-average power usage effectiveness has stood still for six years at about 1.54; the best operator has stood still since 2018 at about 1.09. Universal adoption of best-in-class practice is a 29% one-off. There is a further caveat that cuts the other way and should be stated: the survey panel behind the industry average has been gradually expanded into territories where ambient conditions are more taxing on cooling, so the flat line somewhat overstates technical stagnation. The direction of the correction does not change the size of the remaining prize.

Established The fourth binds every exotic alternative and binds it in the same place: the system boundary. Superconducting logic pays 352 to 3,520 times for refrigeration and loses. Analogue in-memory pays at the analogue-to-digital converters and at the host that runs the layers the array cannot. Neuromorphic inference pays at the memory hierarchy the moment a model does not fit in on-chip SRAM. Thermodynamic sampling has not yet published a system boundary at all. The pattern is consistent enough to be a design rule: a device-level advantage survives to the wall only if the plant, the conversion and the host it requires are smaller than the advantage, and they usually are not.

Frontier The fifth is measurement, and it is more binding than it looks. The neuromorphic field states in a peer-reviewed venue that it lacks standardised benchmarks and that the validity of its solutions cannot currently be directly quantified. No hyperscaler has published a measured training-versus-inference energy split. No thermodynamic device has a measured end-to-end figure. No independent audit of industry-average power usage effectiveness exists. A field that cannot compare its options cannot allocate capital between them, and the effect is that money follows whoever publishes the largest simulated multiplier.

Frontier The sixth is not a bottleneck on efficiency but on demand realisation, and it may be the one that decides the terawatt-hours. Interconnection queues are not order books. A grid-software chief executive puts it at “five to 10 times more interconnection requests than data centers actually being built.” A September 2024 survey of twenty-five large utilities found that among the ten where data centre requests already accounted for at least half of present peak load, none expected an actual five-year share above 35%. One hyperscaler cancelled up to 2 GW of capacity reservations in the first months of 2025. Duplicate filings and phantom load are documented. Flagged frontier because what these facts imply about outturn is an inference, not a measurement — but any forecast built on queue volume is building on a number that the queue's own participants do not treat as a commitment.

Established What is not a bottleneck, stated plainly. The thermodynamic limit is not binding on anything anyone is building, and will not be within the horizon of this brief. Cooling technology is not binding. Neither is the availability of a clever device concept: there are more credible architectures than there are credible measurements of them. The scarce inputs are electricity, system-level energy accounting, and time.

Established Three photonic bottlenecks are manufacturing rather than physics, and they behave differently from the CMOS constraints elsewhere in this brief. The first is the laser. Silicon does not lase efficiently, so light comes from III-V material bonded onto the photonic die or delivered through a fibre. Frontier A laser also draws its power whether or not any computing is happening, so an optical system has a floor its digital competitor does not, and its efficiency advantage shrinks as utilisation falls — the opposite of the duty-cycle assumption most energy comparisons make silently. Established The second is thermal. A silicon microring shifts its resonance by of order 50 to 80 pm per kelvin, so every ring needs an integrated heater and a control loop to stay on wavelength. Frontier Per-ring heater power is reported in the milliwatt range, which means a large mesh can spend more power holding itself in tune than performing the arithmetic it was built for. Established The third is packaging: fibre attach demands sub-micron alignment, and packaging and test dominate photonic unit cost as they do not for digital logic.

Established Nothing in this brief waits on a physics result, and saying so is the point. The bound is known to four significant figures, the distance to it is characterised at several definitions of an operation, the reachable engineering ceiling has been estimated independently, and the experiments that test the bound have been run in three different substrates. What the field waits on is engineering, accounting and demand.

Established It depends on CMOS device and interconnect engineering, which is the only remaining mechanism of the four that delivered the flat-energy decade. Interconnect capacitance and leakage are where the energy goes, and both are process and circuit problems rather than discoveries. The bound on this dependency is the 200× figure with even odds of stopping short.

Established It depends on refrigeration efficiency for one whole branch of the alternatives. Superconducting logic's fate is decided by the Carnot fraction of the cryoplant, not by the junction: the difference between an inverse efficiency of 352× and 3,520× is the difference between an argument worth having and one that is settled. That dependency runs into high temperature superconductors and superconducting infrastructure for the materials and the plant, and this brief takes their numbers rather than generating its own.

Frontier It depends on benchmark standardisation before any of the alternatives can be chosen between. This is an unusual dependency to record because it is epistemic rather than technical, but the neuromorphic field has stated in print that the validity of its solutions cannot currently be directly quantified. Until a common benchmark exists at a fixed system boundary, capital allocation in this area is being made on incomparable numbers.

Established What depends on it is the more consequential direction. Computing has become a first-order load on electricity systems, which places it upstream of storage, firm generation, geothermal and transmission planning rather than beside them — and the largest contracted volumes in several of those sectors have gone to computing buyers rather than to utilities. It also constrains artificial general intelligence scaling assumptions arithmetically: a scaling plan that assumes cheap compute is assuming a rate of efficiency improvement this brief bounds.

Established Landauer's bound has been experimentally approached, and the record is better than the phrase “purely theoretical” suggests. The 2012 peer-reviewed demonstration used a single colloidal particle in a double-well optical trap and found that the mean dissipated heat saturates at the Landauer bound in the limit of long erasure cycles. The approach is asymptotic in cycle duration: fast erasure dissipates more, which is the first sign that the bound is a limit on a quasistatic idealisation rather than a specification for hardware. A 2016 result took it into a real nanoscale digital memory bit — nanomagnetic cells — measuring 6.09 ± 1.43 zJ at 300 K, or 1.45 ± 0.35 k_BT against a bound of 0.69 k_BT. About twice the limit, in a device rather than an apparatus.

Established The 2026 result is the one that should lead, and it complicates the story rather than confirming it. A March 2026 peer-reviewed measurement of erasure energy efficiency in silicon DRAM cells, using single-electron charge counting, found two things. First, efficiency decreased as the erasure error probability decreased — the reliability-versus-energy trade-off is not a theoretical curiosity but a measurable property of a shipping memory technology. Second, the Landauer limit was not achieved even under prolonged operation, because DRAM cells cannot prepare initial states in thermal equilibrium and therefore cannot operate quasistatically. So the honest answer to whether Landauer has been verified is: yes, in bespoke physics apparatus, to within about a factor of two — and the first attempt to measure it in an actual memory technology found a tighter practical constraint arising from the device architecture itself. The exact numerical factor above kT ln 2 in that experiment is not stated in the accessible abstract, and this brief does not supply one.

Established The most useful natural experiment is one company's annual accounts. A hyperscaler's own disclosures for the same year report a 33-fold reduction in energy per median text prompt and a 37% increase in total electricity consumed, the largest load growth in its history. No experiment anyone could design would test the rebound proposition more directly, and none is available at all in the econometric literature: the pack found no published quantified rebound elasticity for computing anywhere. The principal 2025 academic treatment is conceptual, argues that assessing rebound requires combining lifecycle assessment with socio-economic analysis, and supplies no elasticity estimate.

Frontier The second natural experiment is already running in utility interconnection queues. The gap between requests filed and plants built is being measured in real time by the utilities themselves, and the five-year expectations they report are far below the queue volumes they hold. Watching whether the 2028 to 2030 outturn lands nearer the low end of published ranges than the high end is a live test of whether the forecasting literature has again mistaken announced intent for demand.

Established Two negative results worth recording, because absence of a number is a finding. The intergovernmental agency's flagship electricity reports for 2026 — both the annual demand chapter and the mid-year update — carry no data centre terawatt-hour figures at all; those live in a separate AI-specific report series. And Ontario's system planner, in its 2026 Annual Planning Outlook, publishes no quantified data-centre load forecast: data centres appear inside a “growth margin” category under economic development, described as commercial artificial-intelligence service-providing data centres with different likelihood factors across scenarios, with no data-centre-specific breakdown of the connection queue.

Frontier The experiments that would settle the open questions have not been run, and each is cheap relative to what is being spent on the hardware. A measured joules-per-sample figure from a fabricated thermodynamic chip on any real workload. An absolute energy-per-operation comparison between a reversible test chip and a conventional part at the same node. A net-of-refrigeration system analysis of superconducting logic on 2025–26 hardware, which does not exist — the most recent quantitative treatment is a decade old. A measured training-versus-inference split from any operator. And a standardised neuromorphic benchmark suite with published energy at a fixed system boundary, which the field's own benchmarking effort exists to build and has not yet delivered.

Established Where a chip's energy actually goes is the first thing the Landauer framing obscures. Erasure is a small part of the budget. The dominant terms are charging and discharging interconnect capacitance — moving a bit across a chip costs about 600 fJ against about 150 fJ to perform a 16-bit floating-point operation, so communication costs roughly four times computation — and static leakage, which dissipates whether or not anything is computed. Neither term is thermodynamically required. Both are consequences of using voltage on capacitive wires to represent information at room temperature, and both are what a 200× engineering ceiling is a ceiling on.

Established The distances to the bound, stated with their basis. The table below is the pack's energy figures with this brief's arithmetic for the ratios. Every entry is a different definition of “an operation,” which is why quoted Landauer multiples in circulation range across four orders of magnitude without anyone being wrong.

Established Power usage effectiveness is a ratio, and the ratio hides more than it reveals. It is total facility energy divided by energy delivered to the computing equipment, so a value of 1.54 says that about a third of site energy is overhead. What it does not say is anything whatever about what the computing equipment does with its share. A site running maximally wasteful hardware at PUE 1.05 scores better than a site running efficient hardware at PUE 1.30 while consuming more electricity for the same delivered work. Worse, the metric moves the wrong way under good practice: retiring idle servers reduces IT load and therefore raises PUE, while adding power-hungry accelerators lowers it. The industry body that publishes the series draws the correct conclusion itself — the energy performance of digital infrastructure “hinges primarily on the efficiency of IT, not facilities.”

Established The demand numbers, with boundaries, because the boundary is the disagreement. The table below shows why two credible estimates of the same period differ. The 2023 intergovernmental review figure explicitly excludes cryptocurrency; the 2024 and 2025 figures from a different report series in the same organisation use a somewhat broader boundary. The series do not splice cleanly and this brief reports rather than smooths that.

Established Regional and equipment splits, where they exist. The 2024 regional distribution is roughly 45% United States, 25% China and 15% Europe. Within a data centre, servers account for about 60% of electricity, cooling for 7 to 30% depending on climate and design, storage for about 5% and networking for about 5%. Accelerated servers are growing at about 30% a year against 9% for conventional servers and account for almost half the net increase. For the United States specifically, a national laboratory reports 60 TWh (1.8% of national electricity) in 2014, 76 TWh (1.9%) in 2018, and 176 TWh (4.4%) in 2023.

Frontier Per-query AI energy is now measured rather than guessed, and the two best figures agree. A production measurement of a median text prompt gives 0.24 Wh and 0.26 mL of water, on a boundary that explicitly includes active accelerator power, host system energy, idle machine capacity and facility overhead — the idle-capacity inclusion is what makes it credible rather than cherry-picked. An independent bottom-up model of frontier models above 200 billion parameters on H100 nodes gives a median 0.31 Wh per query, interquartile range 0.16 to 0.60 Wh, and concludes that existing public estimates are overstated by four to twenty times. A measured 0.24 and a modelled 0.31 converging is the strongest agreement in this literature. Both parties are interested; both are reporting numbers lower than the ones circulating about them, which is at least not self-serving in the usual direction.

Established The median is the wrong statistic, and the spread across modalities is the real story. Independent measurements on open models give 57 J of GPU energy, about 114 J total, for an 8-billion-parameter model, rising to 3,353 J GPU and about 6,706 J total at 405 billion parameters; roughly 1,141 to 4,402 J for a diffusion image; and about 3.4 MJ for a five-second video. Test-time scaling compounds it: queries fifteen times longer raise median energy thirteenfold, to 3.91 Wh with an interquartile range of 2.15 to 7.05 Wh. A median text prompt is roughly four orders of magnitude below a short video. Any per-query figure quoted without the modality and without the distribution is close to meaningless.

Established Fabrication is the solved part of the photonic story. Silicon photonics runs on CMOS-compatible 300 mm lines with commercial process design kits, so waveguides, modulators and detectors are a manufacturable library rather than a laboratory craft. Frontier The design stack around them is not: no standard-cell equivalent, and no mature analysis flow for optical crosstalk and thermal coupling at mesh scale. Frontier Weights set by thermo-optic tuning reconfigure on microsecond-to-millisecond timescales and drift with die temperature. Speculative A processor whose weights are expensive to change is an inference appliance, and pricing it against a general-purpose accelerator on joules per operation compares two different products.

Biological computing is adjacent in the shared premise that a different substrate might escape the current numbers, and this brief's method transfers to it directly: ask what was measured, on what workload, at what system boundary. On present evidence the answer for biological substrates is the same as for thermodynamic ones.

High temperature superconductors and superconducting infrastructure are adjacent in the strong sense: superconducting logic's entire energy argument is decided in the cryoplant, which is their subject rather than this one's. The three briefs share a conclusion arrived at independently — that a device with an enormous margin over its physical requirement can still lose at the system level, and that the losing happens in the supporting plant.

Small modular reactors, geothermal megaprojects and energy storage revolutions are adjacent as the supply-side response to the demand this brief measures, and the relationship is now commercial rather than notional: computing buyers, not utilities, have taken the largest contracted volumes in several of those sectors. Anyone modelling their demand is modelling the numbers in this brief whether they intend to or not.

Energy corridors is adjacent as the alternative to all of the above: computation has unusual siting freedom, so moving the load to the power is a live option where moving the power to the load is not. Which of the two wins is a transmission-economics question and belongs there.

Artificial general intelligence is adjacent because this brief supplies a constraint that scaling arguments generally omit. A plan that assumes compute continues to get cheaper at the historical rate is assuming a mechanism that a national laboratory has declared ended and a bounded ceiling of about 200× on what remains.

One neighbour is deliberately not claimed. Commercial fusion is often filed alongside this brief as a supply-side answer to computing demand, but on the timescale over which the 200× ceiling is consumed it is a hope rather than a dependency, and this brief takes no position on it beyond what that brief establishes.

Established The defining institutional fact is that computing has become an energy-system actor and is being courted as one. The firm-generation sectors examined elsewhere on this map — small modular reactors, geothermal megaprojects — now aim a large share of their commercial case at data-centre demand, and the largest contracted volumes in both have gone to computing buyers rather than to utilities. A load that signs power purchase agreements at that scale is not a customer of the electricity system; it is a participant in its planning.

Established The institution that measures does not exist. The industry-average efficiency series is a self-reported, unaudited survey run by an industry body; its own analysts note that the panel has been expanded into hotter climates, which changes the series. The only apparently independent corroboration is a national-laboratory model rather than a measurement. No regulator, standards body or auditor collects verified energy performance from data centres at national scale in any jurisdiction this brief examined. For a sector approaching 500 TWh a year of global consumption, that is a remarkable gap.

Established The institution that forecasts has a documented record and an unusual recent stability. The intergovernmental agency's central 2030 projection of 945 to 950 TWh was explicitly left unrevised across 2025 — its December 2025 update states that the central projection remains close to the trajectory set out earlier — in a year when the outturn grew 17%. Meanwhile the wider literature's 2030 projections span from just over 200 TWh to nearly 8,000 TWh, with modelling approach a good predictor of assessment quality and temporal-proxy extrapolation considered low quality beyond two or three years. Where the number comes from matters more than what it is.

Established An institutional oddity worth recording: the flagship electricity reports do not carry the number. The same agency's 2026 annual electricity demand chapter and its 2026 mid-year update contain no data centre terawatt-hour figures, though the demand chapter attributes roughly half of United States demand growth to 2030 to data centres. The figures live in a separate AI-specific report series. A reader consulting the flagship electricity publication for the sector's consumption will not find it, which shapes who cites what.

Established Utilities do not believe their own queues, and have said so on the record. A September 2024 survey of twenty-five large utilities found that among the ten where data centre requests already accounted for at least half of present peak load, none expected an actual five-year share above 35%. Independent commentary puts it at five to ten times more interconnection requests than data centres actually built; duplicate filings and phantom load are documented; and one hyperscaler cancelled up to 2 GW of capacity reservations in early 2025. The interconnection queue is the most-cited demand evidence in public debate and the least reliable, and no institution audits it.

Established The Canadian finding is a negative one and it belongs here. Ontario's system planner, in its 2026 Annual Planning Outlook, publishes no quantified data-centre load forecast. Data centres appear inside a “growth margin” category under economic development, described as commercial artificial-intelligence service-providing data centres, carried with different likelihood factors and confidence levels across scenarios, and with no data-centre-specific breakdown of the connection queue. For a brief asking whether this is an energy-system problem, the fact that Canada's largest provincial system operator does not report the number separately is itself the finding. The scope of that finding should be stated honestly: only Ontario was checked. Hydro-Québec, BC Hydro, the Alberta Electric System Operator, the Canada Energy Regulator and Statistics Canada were not, and a dedicated pass would probably find more — though the Ontario result suggests what it would find is that nobody in Canada publishes this either.

Frontier The unresolved institutional question is whether efficiency regulation is the right instrument at all. If gains are reinvested in more computation — and the one clean firm-level data point says they are — an efficiency standard changes what is computed rather than what is consumed. The instrument that binds consumption is one that prices the electricity or constrains the connection, and that is a jurisdictional decision nobody has yet made about a load that can relocate to whichever jurisdiction declines to make it.

Almost every efficiency number in this field is published by a party selling something, and the brief says so rather than pretending otherwise. Established The power-usage-effectiveness series is compiled by an industry body from self-reported, unaudited returns. The best facility figure comes from the operator it flatters. The two best per-query measurements come from the two firms whose consumption is under most scrutiny. The neuromorphic, analogue, reversible and thermodynamic figures come, without exception, from the organisations building the hardware or from trade press reporting their announcements. This does not make any of them wrong. It does mean that this brief marks interested parties in its reading list, relies on peer-reviewed and intergovernmental sources for every headline figure it treats as established, and takes vendor numbers for facts a vendor would be embarrassed to get wrong rather than for framing.

Established There is no independent audit of computing energy performance anywhere, and the two apparently independent confirmations are not independent. The industry survey gives 1.54 for 2025; a national laboratory's model gives roughly 1.54 for 2023. The second is a model, not a measurement, so the agreement is weaker than it looks. A sector consuming approaching 500 TWh a year has no auditor, and the absence is a policy failure rather than a technical one.

Established Research integrity here is a problem of amplification rather than of fraud. The archetype is a peer-reviewed paper in a prestigious journal reporting a 70,000-fold energy reduction that its own methods describe as device-level simulation, with nothing fabricated. Nobody misrepresented anything; the qualification is in the paper. But a number of that size, in a venue of that standing, will be repeated without the qualification for years. The obligation this creates falls on secondary writers, including this one: report the measurement, the workload and the system boundary together, or do not report the multiplier.

Frontier Public money is entering this area faster than the evidence base supports. A reported letter of intent worth $75 million between a thermodynamic computing company and a national commerce department is referenced in the pack but was not fetched and is unverified here; it is named rather than relied upon. What can be said is that the thousand- and ten-thousand-fold claims attached to that class of company are projections and simulations, and that public deliberation about whether to fund them is proceeding on numbers that have no measured end-to-end counterpart.

Frontier The opportunity cost runs the other way from where attention is. Exotic architectures absorb research funding and coverage on the strength of device-level multipliers, while the measured levers — a 29% one-off in facility overhead, a bounded 200× in CMOS, and demand-side policy that prices electricity rather than mandating efficiency — are unglamorous and quantified. If rebound is real at sector scale, efficiency spending has a smaller effect on consumption than pricing does, and that is a normative claim this brief holds tentatively rather than confidently, because no quantified rebound elasticity for computing exists in any source consulted.

What this brief does not know, stated as an obligation. No measured training-versus-inference energy split exists from any operator. No system-level superconducting energy analysis including cryogenic overhead has been published since 2016. The exact numerical factor above kT ln 2 in the 2026 DRAM experiment is not stated in the accessible abstract and is not supplied here. The canonical energy-per-operation reference table could not be obtained, so the per-operation figures in this brief rest on a single non-peer-reviewed research-institute source and should be treated as the weakest link in it. And on the Canadian question the brief has checked one province only.

Frontier Computation is the first industrial load in a long time to grow fast enough to reshape electricity planning, and it does so with unusual siting freedom. Most large loads are tied to a place by ore, water, port or population. This one can be built where the power is, which makes it a genuinely new object for planners: a demand that negotiates rather than appears, and that can leave.

Established The general principle this case illustrates is that the device is never the system, and it generalises well beyond computing. Superconducting logic wins at the switch by five orders of magnitude and loses at the wall by up to thirty, entirely through the plant required to hold it in its winning regime. The same structure appears in analogue arrays that lose at the converters, in inference chips that lose the moment the model exceeds on-chip memory, and in thermodynamic sampling that has not yet drawn a system boundary at all. Wherever a technology is advocated on a device-level figure of merit, the question that decides it is what the supporting plant costs — and that question is usually answerable and usually not asked.

Established The second principle is that a transition is not a trend, and mistaking one for the other made a decade of policy. The flat-energy decade from 2010 to 2018 was produced by virtualisation, hyperscale migration and falling facility overhead, all of which have endpoints and all of which have reached them. The result was read as a law about computing rather than as the exhaustion curve of three specific migrations, and forecasts built on it under-predicted the next transition badly. Any efficiency story whose mechanism is a one-time reorganisation should be dated, not extrapolated.

Frontier The third is rebound, and computing supplies the cleanest instance available in any sector. A 33-fold improvement in energy per unit of service and a 37% increase in absolute consumption, in the same firm in the same year. If that relationship holds at sector scale, efficiency regulation changes what is computed rather than how much electricity is consumed, and the instrument that binds consumption is one that prices the electricity.

Speculative What would have to be true for this to stop being an energy-system problem. Demand growth would have to fall to roughly the rate of efficiency improvement — that is, from 13 to 17% a year to low single digits — or a non-CMOS architecture would have to deliver a system-level win large enough to buy a decade. Nothing in the current evidence suggests either. This is flagged speculative because it is a conditional about a demand curve, and demand curves in this sector have surprised every forecaster in both directions.

Established What already happened, because this timeline usually starts in 2023 and the interesting part is earlier. In 2007 the United States Congress was warned that data centres could account for a third of national energy use by 2030; the outturn was off by roughly an order of magnitude, and the analyst who documented the overshoot attributed it to the financial crash plus efficiency work. Between 2010 and 2018 compute rose more than 550% while global data centre electricity went from 194 TWh to 205 TWh. Then the direction of the error reversed: between 2017 and 2023 United States data centre demand more than doubled, reaching 176 TWh and 4.4% of national electricity, driven by accelerated servers that the flat-energy consensus had not modelled. Global figures reached 415 TWh in 2024 and 485 TWh in 2025, the latter a 17% rise with AI-specific facilities up 50%.

Established The device milestones of 2025 and 2026, in order. January 2025, a reversible-computing tape-out announced with a simulated 50% resonator recovery; May 2025, chips in transit from fabrication with the claim not independently verified; August 2025, a thermodynamic chip taped out with a projected but unmeasured thousandfold claim; September 2025, the first measured reversible recovery factors of 1.77× and 1.41× on 22 nm silicon at 500 MHz; September 2025, a peer-reviewed superconducting review that declines to publish a net-of-cooling energy comparison; December 2025, a thermodynamic preprint whose ten-thousandfold figure rests on a simulated architecture and a binarized Fashion-MNIST benchmark; March 2026, the first erasure-efficiency measurement in silicon DRAM cells.

Frontier To 2028 and 2030: the projections, with their spread stated. The intergovernmental base case is 945 to 950 TWh by 2030, about 3% of global electricity, rising to about 1,200 TWh by 2035 with a 2035 case range of 700 to 1,700 TWh; its December 2025 update states explicitly that the central projection remains close to the trajectory set out earlier, meaning it has not been revised in either direction across 2025. For the United States alone, a national laboratory projects 325 to 580 TWh by 2028, or 6.7 to 12.0% of national electricity; an NGO analysis puts United States 2030 at 200 to 1,050 TWh with a 300 to 400 TWh consensus; an industry research institute's range for 2030 is 383 to 793 TWh. These are not variants of one forecast. They are different scopes and different methods, and the honest summary is that the United States 2030 number is not known within a factor of five.

Handwave Any 2030 figure quoted without its method. The published literature's 2030 projections span from just over 200 TWh to nearly 8,000 TWh, a fortyfold spread. Studies rated low quality span 480 to 2,000 TWh; studies rated high quality span 190 to 560 TWh. Modelling approach is a good predictor of assessment quality, and temporal-proxy extrapolation is considered low quality beyond two or three years. A number's provenance is more informative than its value.

Handwave Device roadmaps beyond the current silicon. A 4,000× reversible-computing target described by its own trade coverage as ten or fifteen years out; a thermodynamic roadmap running from high-resolution diffusion to video diffusion on unmeasured hardware. These are intentions and this brief records them as such.

Frontier The milestone that would actually change the argument, and which nobody has scheduled. A published system-level energy win — refrigeration, conversion and host overhead included — by any non-CMOS architecture on a real workload. None exists. It requires no breakthrough to attempt and no organisation has published one, which is itself the most informative fact in this section.

Frontier The photonic horizons, kept separate because optical I/O and optical computing resolve at different times:

• 10 yr: Frontier Co-packaged optics becomes ordinary in large-cluster networking, and an independent measurement of a co-packaged switch against a pluggable one at the wall either confirms the vendor multipliers or never appears. Speculative Optical computing ships in narrow inference and optimisation niches or does not ship at all, decided by packaging yield rather than by any physics result.
• 25 yr: Speculative Either a system-level benchmark exists that measures joules per token with the laser and the converters inside the boundary, or the field keeps reporting device-boundary ratios and stays unfalsifiable. Frontier Photonics inherits this brief's named benchmark constraint unchanged.
• 50 yr and beyond: Handwave Any claim that computation is predominantly optical at this horizon is an assertion about manufacturing economics that nobody can currently support. Speculative The defensible long-run statement is that data movement keeps migrating to light and arithmetic stays with the transistors unless conversion overhead is solved.

• Depends on Nothing on this map. The thermodynamic bound is known, the distance to it is characterised at several definitions of an operation, and the reachable engineering ceiling has been estimated independently — so nothing here waits on a physics result. That is the cleanest statement of this topic's position: a room-temperature miracle in device physics would be welcome and its absence is holding nothing up, because the binding variable is a demand curve.
• Requires (not on this map) Device and interconnect engineering within CMOS, where the remaining reachable improvement is about 200× with even odds of stopping short. Cryocooler efficiency, which alone decides whether superconducting logic is three times worse than CMOS at the wall or thirty. Analogue-to-digital conversion and peripheral overhead reduction, named by the tile designers themselves as the unresolved gap between tile-level and system-level efficiency. Standardised system-level energy benchmarks, absent by the field's own admission and the reason its claims cannot be compared. The rate of compute demand growth, which is a market question and the most decisive of the six. And an institution capable of independently measuring and auditing energy performance, which does not exist — the power-usage-effectiveness series is self-reported and unaudited, and the only independent check on it is a model rather than a measurement. A seventh requirement arrives with the optical module and does not change that ranking: photonic packaging — laser integration, fibre attach and the test flow around them — which is where photonic cost and yield are decided, and is an industrial capability rather than a research question.
• Enables Nothing typed. Computation is an input to most of this map rather than an output of it, and claiming enabling edges to every brief that assumes compute generically would overstate what any of them depends on.
• Adjacent Biological computing, sharing an interest in radical substrates; high temperature superconductors and superconducting infrastructure, since superconducting logic is decided by refrigeration rather than by the switch; energy storage revolutions, small modular reactors and geothermal megaprojects, all now marketed substantially to this load; energy corridors, because siting computation near generation is the alternative to moving power to it; and artificial general intelligence, whose scaling assumptions this arithmetic constrains.

“We are a hundred million times above the Landauer limit, so there is enormous headroom.” Handwave Distance from Landauer is not headroom, and treating it as such is the central error in this subject. The gap is real — roughly 10⁵ per elementary gate switching event and 10⁸ per useful whole-chip floating-point operation — but the reachable CMOS ceiling is about 200×, with even odds of stopping short of it. The gap between what physics permits and what engineering can reach is itself about six orders of magnitude, and every one of them is unreachable in practice. Quote both numbers together or the sentence will be misread.

“The Landauer limit is the energy floor for computing.” Established It is the floor for logically irreversible bit erasure only. It bounds neither an arithmetic operation nor the movement of data, and moving a bit across a chip — about 600 fJ, against about 150 fJ for a 16-bit floating-point operation — is where a large share of the energy actually goes, alongside static leakage that dissipates whether or not anything is computed. Neither term is thermodynamically required. A brief that treats kT ln 2 as the target is aiming at the wrong quantity.

“Landauer has been experimentally verified, so the limit is the relevant constraint on memory.” Established Verified in bespoke apparatus, to within about a factor of two: a colloidal particle in an optical trap saturating the bound asymptotically in long erasure cycles, and nanomagnetic bits at 6.09 ± 1.43 zJ against the 2.87 zJ bound. But the first measurement in an actual memory technology — silicon DRAM cells, March 2026, single-electron charge counting — found that the limit was not achieved even under prolonged operation, because DRAM cells cannot prepare initial states in thermal equilibrium and so cannot operate quasistatically. It also found that erasure efficiency falls as error probability falls. In real memory the binding constraint is tighter than kT ln 2 and it is architectural.

“Power usage effectiveness measures data-centre efficiency.” Established It is a ratio, and the ratio hides more than it reveals. Facility energy divided by computing energy says nothing whatever about what the computing equipment does with its share: a site running wasteful hardware at 1.05 scores better than a site running efficient hardware at 1.30 while drawing more electricity for the same work. The metric also moves the wrong way under good practice — retiring idle servers cuts IT load and therefore raises PUE. On top of that, part of the observed plateau at 1.54 is a sampling artefact: the survey panel behind it has been expanded into territories where ambient conditions are more taxing on cooling, so the flat line overstates technical stagnation somewhat. The publishing body's own conclusion is the right one: energy performance “hinges primarily on the efficiency of IT, not facilities.”

“Better cooling will fix data centre energy.” Established Industry-average power usage effectiveness is 1.54 and has been flat for six years; the best operator is at 1.09 and flat since 2018. If the entire global fleet became the best operator tomorrow, global data centre electricity would fall 29% — about 2.2 years of growth at the 2025 rate. The arithmetic is this brief's; the inputs are sourced. It is a real prize and it is a one-off.

“Data centre forecasts always run hot.” Established The direction of error has reversed, and this is the correction most often missed. Pre-2020 forecasts did overshoot badly: Congress was warned in 2007 that data centres could reach a third of United States energy use by 2030; one 2019 study projected 650 to 900 TWh for 2020 against a subsequent high-quality range of 200 to 350; a 2015 study projected 400 to 1,700 TWh for 2022 and its own authors later revised to 200 to 550. But the 2018–2020 consensus of continued flat energy under-predicted the accelerator ramp, and United States demand more than doubled between 2017 and 2023. “Forecasts run hot” is not a safe prior. The safe statement is that the errors have been large in both directions and have always occurred at discrete technology transitions that nobody modelled.

“Global data centres use X terawatt-hours.” Established Not without a boundary. A credible intergovernmental review gives 300 to 380 TWh for 2023 excluding cryptocurrency; a different report series in the same organisation gives 415 TWh for 2024 on a broader boundary, and the two do not splice cleanly. Whether the figure includes networks, crypto mining, embodied hardware energy or idle reserve capacity changes it substantially. For 2030 the published literature spans just over 200 TWh to nearly 8,000 TWh — a fortyfold spread — with low-quality studies clustering at 480 to 2,000 and high-quality studies at 190 to 560. Method predicts quality. A figure without a stated boundary, year and method should be treated as uninterpretable.

“Superconducting logic is vastly more energy-efficient.” Established At the device, by up to five orders of magnitude: 0.25 aJ per junction switch against 100 aJ to 100 fJ per CMOS gate. At the wall, after a cryogenic inverse efficiency of 352 to 3,520 times, a worked billion-junction processor draws 250 W to 2.5 kW against the CMOS equivalent — three to thirty times worse — and measured floating-point units come out at 0.12 to 1.3 GFLOP/J against CMOS at 2.27. Frontier There is one counter-claim and this brief reports it rather than burying it: an adiabatic quantum-flux-parametron processor switching at 1.4 zJ per junction, claimed at about 80 times more efficient than semiconductors including cooling — demonstrated at 100 kHz, four to five orders of magnitude below a CMOS clock, and dating from 2020. The two accounts are not reconciled here.

“Nothing exists in reversible computing.” Established That would now be wrong. There is measured silicon: a 22 nm test chip at 500 MHz with energy recovery factors of 1.77× for a capacitor array and 1.41× for a shift register, fabricated and tested in 2025. Give it the credit and then note the distance: no absolute energy-per-operation comparison against a conventional part has been published, and the widely repeated “about 30% less energy than a standard processor” is the 1.41× recovery restated, not a second result.

“Neuromorphic chips are orders of magnitude more efficient.” Frontier On particular workloads, against general-purpose parts doing something they are poor at, and the field says so itself: a peer-reviewed benchmarking paper with more than eighty authors states that the field lacks standardised benchmarks and that the validity of neuromorphic solutions cannot be directly quantified without them. The best-known headline figure of 15 TOPS/W is measured on a synthetic multi-layer perceptron stimulated with random noise, with 10:1 sparsity and 10% activation rates; the accompanying “100 times less energy, 50 times faster” names no workload at all, and the system is described by its builder as a research prototype. The honest description of the genuine gains is specialisation, not brain-likeness.

“Analogue in-memory computing gives tens of thousands of times better efficiency.” Frontier The 70,000-fold figure comes from a peer-reviewed Nature-family paper that states it used device-level simulations; nothing was fabricated. The best measured chip in the same family reports 12.4 TOPS/W falling to 6.94 as a full-system estimate, with a real accuracy cost and with the host running the layers the array cannot — roughly a two- to fivefold advantage over an H100 at INT8. Tile-level TOPS/W is not system TOPS/W, and the tile designers say so themselves.

“Thermodynamic computing is ten thousand times more efficient.” Handwave The probabilistic circuits are real and measured; the multiplier is not. The figure comes from a preprint combining measurements from a random-number-generator chip with physical models and simulations, in which the evaluated architecture is simulated and the workload is binarized Fashion-MNIST image generation; the company's own writing says “could be… as shown by our simulations,” and its hardware page gives no energy per sample. A competing thousandfold claim is projected from a chip that had not been characterised at announcement. As of the research date no thermodynamic device has published a measured end-to-end energy figure on any real workload.

“Eighty to ninety percent of AI computing energy goes to inference.” Handwave This is the most-repeated statistic in the field and it has no traceable source. It appears in trade press as an estimate with no measurement and no named origin; the intergovernmental agency's own chapter on AI energy demand gives no training-versus-inference split at all, offering only equipment shares and growth rates; the 2025 national-academies workshop proceedings define the terms and give no split. No hyperscaler has published a measured split. This is a genuine gap, not a settled fact.

“An AI query uses roughly X watt-hours.” Established A measured median text prompt is 0.24 Wh on a boundary including idle capacity; an independent bottom-up model gives 0.31 Wh median with an interquartile range of 0.16 to 0.60, and concludes existing public estimates are overstated by four to twenty times. But the median is the wrong statistic. Fifteen-times-longer queries raise median energy thirteenfold to 3.91 Wh; measured open models range from about 114 J total at 8 billion parameters to about 6,706 J at 405 billion; a diffusion image is 1,141 to 4,402 J and a five-second video about 3.4 MJ. The measured figure has also been criticised for excluding chip manufacturing and indirect water — which can be ten to a hundred times larger than direct use — for being text-only, for hiding the heavy tail behind a median, and for disclosing no query volume and therefore no aggregate.